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SY58626L
DC-to-6.4Gbps Backplane Transmit Buffer with Selectable Output Pre-emphasis, I/O DCOffset Control, and 200mV-3.0VPP Output Swing
General Description
The SY58626L high-speed, low jitter transmit buffer is optimized for backplane and transmission line data-path management applications in Automatic Test Equipment (ATE) and Test & Measurement (T&M) systems. The buffer includes a CML compatible, variable swing output with selectable pre-emphasis. The SY58626L is capable of driving serial data from DC through 6.4Gbps with a 3VPP (1.5VPK single ended) differential swing. The SY58626L differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any DC- or AC-coupled, differential signal as small as 100mVPK without any termination resistor networks in the signal path. The outputs are 50 source-terminated CML with a programmable output swing from 200mVPP to 3VPP (100mVPK to 1.5VPK). The SY58626L includes an output stage that provides 4 levels of pre-emphasis. The output pre-emphasis level is programmed with a three-bit interface. Unlike other transmitter solutions, the output pre-emphasis duration can be programmed from 60ps to 400ps. The SY58626L operates at 3.3V 10% supply and is guaranteed over the commercial temperature range of 0C to +70C. The SY58626L transmitter is optimized to work with the SY58627L receiver. The SY58626L is part of Micrel's high-speed, Precision Edge(R) product line. Data sheets and support documentation can be found on Micrel's website at: www.micrel.com.
Precision Edge(R)
Features
* Transmit driver provides output pre-emphasis to extend transmission range * 4 selectable pre-emphasis levels * Drives 6.4Gbps up to 12" FR4 PCB trace, or longer combinations of FR4+cable+interconnect * DC through 6.4Gbps data rate throughput * Integrated loopback capability * Unique pre-emphasis: - Programmable pre-emphasis magnitude - Programmable pre-emphasis duration * Unique, flexible I/O: - Internal termination to VTTIN pin interfaces to any differential AC- or DC-coupled signals - 50 source terminated CML outputs minimize round-trip reflections - Programmable output swing control: 200mV3.0VPP - Output Disable and output shutdown - DC-offset control with VTT I/O * 3.3V 10% supply voltage * 0C to +70C temperature range * Available in 32-pin (5mm x 5mm) MLFTM package
Applications
* * * * ATE, T&M backplane management Combination FR4+cable+interconnect driver Cable drivers Electrical interface and interconnect applications that require DC-offset control
Precison Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
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SY58626L
Functional Block Diagram
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SY58626L
Ordering Information(1)
Part Number SY58626LMH SY58626LMHTR(2)
Notes: 1. 2. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. Tape and Reel.
Package Type MLF-32 MLF-32
Operating Range Commercial Commercial
Package Marking SY58626L with bar-line Pb-Free indicator SY58626L with bar-line Pb-Free indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
32-Pin MLF
TM
(MLF-32)
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Pin Description
Pin Number Pin Name Pin Function Differential inputs: This input pair is the differential signal input to the device. They accept AC- or DC-coupled signals as small as 100mV (200mVPP). Note that this input will default to an undetermined state if left open. TXIN and /TXIN internally terminate to the VTTIN pin through 50. Please refer to the "Input Interface Applications" section for more details. Input termination center-tap: TXIN and /TXIN terminate to VTTIN. The VTTIN pin provides a center-tap to the internal termination network for maximum interface flexibility and DC-offset capability. Please refer to the "Input Interface Applications" section for more details. Reference voltage: This output biases to VCC -1.3V. It is used for AC-coupling the input pair (TXIN, /TXIN). Connect VREF-AC directly to the VTTIN pin. Bypass with a 0.01uF low ESR capacitor to VCC. Maximum sink/source current is 1.5mA. Due to the limited drive capability, the VREF-AC pin is only intended to drive the VTTIN pin. Please refer to the "Input Interface Applications" section for more details. Analog input that controls TXQ output swing amplitude. The operating range of the control input is from VREF-CTRL (max swing) to VCC (min swing). Control of the output swing can be obtained by using a variable resistor between VREF-CTRL and VCC with the wiper driving TXVCTRL. Output swing ranges from 100mVPK to 1.5VPK. When the TXQ output is selected for maximum swing amplitude of 1.5VPK, no pre-emphasis is possible since the maximum swing cannot extend beyond 1.5VPK. For applications that only require a fixed, full CML swing, connect TXVCTRL to VREF-FIXED. Reference control voltage for TXVCTRL swing control. The operating range of the control input is from VREF-CTRL (max swing) to VCC (min swing). Control of the output swing can be obtained by using a variable resistor between VREF-CTRL and VCC with the wiper driving TXVCTRL. Maximum sink/source current is 1.5mA. Reference output voltage: Connect this reference output pin directly to the TXVCTRL input pin, and the TXQ output swing is fixed to 400mVPK (800mVPP). TTL/CMOS (or VTH controlled) compatible control input for the TXQ Outputs pair. When pulled HIGH, the TXQ Output pair is disabled. This input is internally connected to a 25k pull-down resistor and will default to a logic LOW state (Enable) if left open. When disabled, the TXQ output goes LOW, and /TXQ goes HIGH. Default threshold is Vcc/2 when VTH pin is floating. TTL/CMOS (or VTH controlled) compatible control input for the TXLBQ output pair. When pulled HIGH, the TXLBQ output pair is disabled. This input is internally connected to a 25k pull-down resistor and will default to a logic LOW state (Enable) if left open. When disabled, the TXLBQ output goes LOW, and /TXLBQ goes HIGH. Default threshold is Vcc/2 when VTH pin is floating. Loopback MUX select control: The TTL/CMOS (or VTH controlled) compatible input selects the input to the Loopback mode multiplexer. When LBSEL input is a logic HIGH, the Loopback mode is selected, and the RXLBIN input pair is selected to pass through the TXQ output. Note that the LBSEL pin is internally connected to a 25k pull-down resistor and will default to a logic LOW state if left open (normal operation). The loopback MUX includes internal input isolation to minimize crosstalk. Loopback differential input pair: AC-coupled, CML compatible input. This input pair includes internal termination connected to an internal VBB for an AC-coupled bias configuration. The RXLBIN input pair receives a signal from the RX buffer (SY58627L RXLBQ) loopback output. This input pair does not include any equalization. When Loopback mode is selected, the signal at the RXLBIN input is directed to the TXQ output.
4, 5
TXIN, /TXIN
7
VTTIN
8
VREF-AC
13
TXVCTRL
12
VREF-CTRL
14
VREF-FIXED
24
/TXEN
29
/TXLBEN
1
LBSEL
30, 31
RXLBIN, /RXLBIN
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SY58626L
Pin Description (Continued)
Pin Number Pin Name TXLBQ, /TXLBQ Pin Function Transmit loopback differential output: CML compatible output pair with 400mV swing into a 50 load (100 across the pair). The TXLBQ output pair is providing a copy of the TXIN input signal, bypassing the pre-emphasis stage. The SY58626L loopback function is optimized to operate with the SY58627L receiver, and the TXLBQ output pair is AC-coupled directly to the TXLBIN input pair on the SY58627L. TXQ shutdown control pin: The TTL/CMOS (or VTH controlled) compatible pin is an active LOW function. This input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. When pulled LOW, the TXQ and /TXQ output currents are shut off, and the TXQ and /TXQ output voltage is set to the same potential. The actual voltage level is set by the resistor divider ratio established by the internal 50 source resistors (connected to VTTOUT) and the external load. Default threshold is Vcc/2 when VTH pin is floating. Input logic threshold control voltage for logic control threshold settings other than LVTTL/CMOS. This input control pin can be externally biased to set the proper threshold for all the logic control pins, /TXEN, LBSEL, /TXLBEN, 3-bit pre-emphasis control, 2-bit pre-emphasis duration control, and /TXQSHDN. For standard LVTTL/CMOS control, simply leave the VTH pin floating and the threshold voltage defaults to VCC/2 (When VEE=0V). For LVPECL thresholds, set VTH to Vcc-1.3V. Differential variable swing output pair: This CML output pair is the output of the device. This output is designed to drive 100mVPK to 1.5VPK into 50 (100 across the pair) with variable pre-emphasis. TXQ outputs include 50 source termination resistors. When the loopback mode is selected, the TXQ output pair is driven by the RXLBIN inputs. Output termination center-tap: Each side of the differential output pair terminates to the VTTOUT pin through 50. The VTTOUT pin provides a center-tap to the output termination network for maximum interface flexibility, and DC-offset capability. Please refer to the "CML Output Interface Applications" section for more details. Pre-emphasis magnitude level control input: TTL/CMOS (or VTH controlled) compatible, 3-bit control interface. There are four levels of pre-emphasis magnitude, as shown in the "Pre-Emphasis Magnitude Truth Table." When MAG_CTRL2 (MSB) is logic 1, pre-emphasis is disabled and the TXQ outputs will not include any preemphasis. Pre-emphasis magnitude ranges from 10% to 33% above the base swing. Pre-emphasis duration control input. TTL/CMOS (or VTH controlled) compatible, 2-bit control interface. This control establishes the pre-emphasis duration. Duration ranges from 60ps to 400ps typical as shown in the "Pre-emphasis Duration Control Truth Table." Pre-emphasis duration is measured from the mid-point of the pre-emphasis magnitude (50% point). Please refer to the "Pre-emphasis Output Description" for details. Positive power supply: Connect to +3.3V power supply. Bypass with 0.1F//0.01F low ESR capacitors as close to VCC pins as possible. Ground: Ground pins and exposed pad must be connected to the same ground plane.
27, 28
23
/TXQSHDN
2
VTH
21, 20
TXQ, /TXQ
19, 22
VTTOUT
17 18 32
MAG_CTRL0 MAG_CTRL1 MAG_CTRL2
10 11
DUR_CTRL0 DUR_CTRL1
9, 15, 26 3, 6, 16, 25
VCC VEE, Exposed Pad
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SY58626L
Pre-emphasis Magnitude Truth Table
Disable Mag Select (MSB=MAG_CTRL2) 0 0 0 0 1 Magnitude Select (MAG_CTRL1) 0 0 1 1 X Magnitude Select (MAG_CTRL0) 0 1 0 1 X Pre-emphasis Magnitude 10% 15% 25% 33% Disabled
Pre-emphasis Duration Control Truth Table
Duration Minimum (Shortest) Medium-short Medium-long Longest DUR_CTRL1 0 0 1 1 DUR_CTRL0 0 1 0 1 DC-3.2Gbps Typical Data Rate 3.2Gbps-6.4Gbps Time Duration 60ps 100ps 200ps 400ps
Pre-emphasis Output Description
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Absolute Maximum Ratings(1)
Supply Voltage (VCC) ...............................................-0.5V to +4.0V Input Voltage (VIN) ...................................................... -0.5V to VCC Input Current (TXIN, /TXIN, 120mins) ................................ 67mA CML Output Current (IOUT) Continuous (120mins)..................................................... 67mA Surge .............................................................................. 100mA Termination Current VT .................................................................................. 100mA VREF-AC Current Source/sink current on VREF-AC.......................................... 2mA Source/sink current on VREF-CTRL ....................................... 2mA Lead Temperature (soldering, 20 sec.) ..............................+260C Storage Temperature (TS) ..................................... -65C to 150C
Operating Ratings(2)
Supply Voltage (VCC) .................................... +3.0V to +3.6V Ambient Temperature (TA) ............................... 0C to +70C (3) Package Thermal Resistance MLF (JA) Still-Air ...............................................................34C/W MLF (JB) Junction-to-Board ..............................................20C/W
DC Electrical Characteristics(4)
TA= 0C to +70C; unless otherwise stated.
Symbol VCC IEE Parameter Power Supply Power Supply Current Max VCC, includes 50 internal source resistors, 1.5VPK output swing, no external load current 45 90 VEE+1.5 VEE+0.7 See Figure 4a. See Figure 4b. 0.1 0.2 1. 28 Voltage applied to VTTIN pin Voltage applied to VTTOUT pin VEE+1.7 VCC-1.5 VCC+0.1 VCC+1.5 Condition Min 3.0 Typ 3.3 290 Max 3.6 370 Units V mA
RIN RDIFF_IN VIH VIL VIN VDIFF_IN VTTIN VTTIN Range VTTOUT Range
Notes:
Input Resistance (TXIN-to-VTTIN) Differential Input Resistance (TXIN-to-/TXIN) Input High Voltage (TXIN, /TXIN) Input LOW Voltage (TXIN, /TXIN) Input Voltage Swing (TXIN, /TXIN) Differential Input Voltage Swing |TXIN-/TXIN| TXIN-to-VTTIN (TXIN, /TXIN) VTTIN Voltage Range VTTOUT Voltage Range
50 100
55 110 VCC VIH-0.1 1.5
V V VPK VPP V V V
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 500lfpm Airflow. TJ < 125C.
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SY58626L
TXQ Outputs DC Electrical Characteristics(5)
VCC = 3.3V 10%; VEE = 0V; TA = 0C to + 70C; RL = 100 across output pair; unless otherwise stated.
Symbol VOUT Range Parameter Output Voltage Range (TXQ, /TXQ) Maximum Swing (TXVCTRL = VREF-CTRL) No pre-emphasis VOUT TXQ Output Voltage Swing (TXQ, /TXQ)(6) Minimum Swing (TXVCTRL = VCC) Fixed Output Swing (TXVCTRL = VREF-Fixed) Maximum Swing (TXVCTRL = VREF-CTRL) No pre-emphasis VDIFF_OUT TXQ Differential Output Voltage Swing |TXQ-/TXQ|(7) Minimum Swing (TXVCTRL = VCC) Fixed Output Swing (TXVCTRL = VREF-Fixed) ROUT VREF-AC VREF-CTRL TXVCTRL ITX QSHDN Output Resistance Output Voltage Reference VREF-CTRL Output Voltage Output Swing Control Voltage Range TXQ Shutdown Leakage Current 650 45 VCC-1.4 VCC-1.4 VREF-AC -500 800 50 VCC-1.3 VCC-1.3 55 VCC-1.2 VCC-1.2 VCC 500 V V V A 325 400 Condition Min VCC-1.5 Typ Max VCC Units V
1500 100 mVPK
3000
200
mVPP
TXLBQ CML Output DC Electrical Characteristics(5)
VCC = 3.3V 10%; VEE = 0V; TA = 0C to + 70C; RL = 100 across output pair; unless otherwise stated.
Symbol VOH VOUT VDIFF_OUT ROUT
Notes: 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 500lfpm Airflow. TJ < 125C. 6. Please refer to figure 4a. 7. Please refer to figure 4b.
Parameter TXLBQ Output High Voltage TXLBQ Output Voltage Swing (TXLBQ, /TXLBQ)(6) TXLBQ Differential Output Voltage Swing (7) |TXLBQ-/TXLBQ| Output Impedance
Condition RL = 50 to Vcc
Min VCC-0.040 325 650 45
Typ VCC-0.010 400 800 50
Max VCC
Units V mVPK mVPP
55
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SY58626L
Logic Control DC Electrical Characteristics(8)
VCC = 3.3V 10%; VEE = 0V; TA = 0C to + 70C; unless otherwise stated.
Symbol VIH VIL VCTRL IIH IIL VTH
Notes: 8. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 500lfpm Airflow. TJ < 125C.
Parameter Input HIGH Voltage Input LOW Voltage Output Swing Control Voltage Range at TXVCTRL Input HIGH Current Input LOW Current Threshold Input Voltage
Condition All control input pins All control input pins
Min VTH+0.2 VEE VREF-CTRL
Typ
Max VCC VTH-0.2 VCC 300
Units V V V A A
-300 Voltage applied to pin (VEE = 0V) 1.4 VCC/2 2.6
V
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SY58626L
AC Electrical Characteristics(9)
VCC = 3.3V 10%; VEE = 0V; TA = 0C to + 70C; RL = 100 across output pair; unless otherwise stated.
Symbol Parameter Condition 1.5VPK output swing, No pre-emphasis 400mV output swing, 33% pre-emphasis 400mV output swing TXIN-to-TXQ (VIN >200mVPK) RXLBIN-to-TXQ tpd Tempco tEN tLB_EN tSHDN tLBSEL tPROG Differential Propagation Delay Temperature Coefficient TXQ Enable/Disable Time TXLBQ Enable/Disable Time TXQ Shutdown Time /TXEN /TXLBEN /TXQ_SHDN HIGH-to-LOW (TXQ Outputs SHUTDOWN) /TXQ_SHDN LOW-to-HIGH (TXQ Outputs ON) LBSEL 3-bit pre-emphasis magnitude, 2-bit duration control update-to-valid TXQ (0,0,0) MAG_CTRL Pre-emphasis Magnitude (Percent beyond base swing) MAG_CTRL (2,1,0) (0,0,1) (0,1,0) (0,1,1) (1,X,X) Minimum (shortest) DUR_CTRL Pre-emphasis Duration DUR_CTRL (1,0) Part-to-Part Skew Random Jitter (RJ) Deterministic Jitter (DJ) tr, tf
Notes: 9. High-frequency AC-parameters are guaranteed by design and characterization. 10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 11. Random jitter is measured with a K28.7 pattern, measured at 6.4Gbps. 12. Deterministic jitter is measured with both K28.5 and 2 -1 PRBS pattern, at 4.25Gbps/6.4Gbps. 13. Contact factory for updated random jitter and deterministic jitter limits.
23
Min DC DC DC 150
Typ
Max 6.4 6.4 6.4
Units Gbps
Freq
Data Rate Throughput (TXQ) Data Rate Throughput (TXLBQ)
Gbps ps ps fs/oC
tpd
Differential Propagation Delay
250 250 120
450
600 200 3 3 350 1 10 15 25 33 0 60 100 200 400 200 Note 13 Note 13 20 50 80 4.5
ps ps ns
4.5 600 ps ns
Loopback Select Time Programming Logic Control Time
%
Medium-short Medium-long Longest Note 10 PE ON, Note 11 PE ON, Note 12 At full output swing
ps
tSKEW tJITTER
ps psRMS psPP ps
Output Rise/Fall Time (20% to 80%)
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SY58626L
Detailed Description
The SY58626L is a high speed, low jitter transmit buffer with integrated loopback capability. Adjustable pre-emphasis amplitudes and selectable pre-emphasis durations are included with the transmitter. The SY58626L also includes disable and shutdown control for the transmitter output. Transmitter The SY58626L transmitter includes the VTTIN and VTTOUT pin for maximum interface flexibility and DCoffset capability for the input and output, respectively. This feature allows for interfacing with different logic families without the use of AC-coupling. The output buffer has internal 50 source terminated CML outputs for minimizing round-trip reflections.
Control of the transmitter output swing buffer can be obtained by using a variable resistor connected between VREF-CTRL and VCC with the wiper driving TXVCTRL. Please refer to Figure 1 for more details.
Transmitter Disable and Shutdown The SY58626L provides two methods to turn off the output when desired. When /TXEN is pulled HIGH, the transmitter output pair is disabled. TXQ goes to a LOW state and /TXQ goes to a HIGH state. When /TXQSHDN is pulled LOW, the transmitter output pair is in shutdown mode. TXQ and /TXQ output currents are shut off and the TXQ and /TXQ outputs are set to the same potential. The threshold for the /TXEN and /TXQSHDN pins is set with the VTH pin. Please refer to the "Typical Operating Characteristics" for more details. Loopback The SY58626L features a loopback test mode, activated by setting LBSEL to logic HIGH. Using the SY58626L with the SY58627L enables local loopback and link side loopback, shown in Figures 2b and 2c. This mode enables an external loopback path, bypassing circuitry on both local and link side. Please refer to Table 1 and Figure 3 for Loopback Control information.
Figure 1. Variable Output Swing Circuit
Transmitter Variable-Swing Output Buffer * Connecting VREF-CTRL to TXVCTRL sets the transmitter output buffer to max swing 1.5VPK (3.0VPP). Connecting VCC to TXVCTRL sets the transmitter output buffer to minimum swing 100mVPK (200mVPP). Connecting VREF-FIXED to TXVCTRL sets the transmitter output buffer to 400mVPK (800mVPP).
Figure 2a. Normal Operation
*
*
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TXLB 0 Normal Mode 0 0 0 Link Side Loopback Mode 1 1 1 1
TXLBENb 0 0 1 1 0 0 1 1
TXENb 0 1 0 1 0 1 0 1
TXQ TXIN 0 TXIN 0 RXLBIN 0 RXLBIN 0
TXLBQ TXIN TXIN 0 0 TXIN TXIN 0 0
Table 1. Transmit Loopback Control Signal Figure 2b. Local Loopback Mode
Figure 3. Loopback Control Pin
Figure 2c. Link Side Loopback Mode
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Typical Operating Characteristics
VCC = 3.3V 10%; VIN > 400mV; TA = 25C, RL = 100 across output pair; unless otherwise stated.
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Typical Operating Characteristics (Continued)
VCC = 3.3V 10%; VIN > 400mV; TA = 25C, RL = 100 across output pair; unless otherwise stated.
Output Disable TXQ /TXQ HIGH /TXQ LOW HIGH LOW Output Shutdown
TXQ
/TXEN
HIGH LOW
/TXQSHDN
Time (250ns/div.)
Time (250ns/div.)
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Single-Ended and Differential Swings
Figure 4a. Single-Ended Voltage Swing
Figure 4b. Differential Voltage Swing
Input and Output Stages
Figure 5a. Simplified Differential Input Stage
Figure 5b. Simplified Differential Output Stage
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Input Interface Applications
option: may connect VTTIN to VCC Figure 6a. LVPECL Interface (DC-Coupled) Figure 6b. LVPECL Interface (AC-Coupled) Figure 6c. CML Interface (DC-Coupled)
Figure 6d. CML Interface (AC-Coupled)
Figure 6e. LVDS Interface (DC-Coupled)
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CML Output Interface Applications
Figure 7a. CML DC-Coupled Termination
Figure 7b. CML DC-Coupled Termination
Figure 7c. CML AC-Coupled Termination
Related Product and Support Information
Part Number SY58627L Function DC-to-6.4Gbps Backplane Receive Buffer with 4Stage Programmable Equalization and DC-Offset Control MLFTM Application Note HBW Solutions New Products and Applications Data Sheet Link www.micrel.com/product-info/products/sy58627u.shtml
www.amkor.com/products/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
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32 Lead MicroLeadFrameTM (MLF-32)
Package Notes: 1. Package meets Level 2 Moisture Sensitivity Classification. 2. All parts are dry-packed before shipment. 3. Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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